Canonization of graphs during transistor circuits decompilation

نویسندگان

چکیده

Objectives. The objective of the work is to develop means for recognition (extraction) high-level structures in circuits on transistor level. This allows obtain a representation logical level, equivalent original flat description Obtaining such significantly reduces time perform VLSI topology check, but also provides basis reengineering integrated and reverse engineering detecting unauthorized attachments. Methods. Graph based methods software tools are proposed recognizing topologically circuits, which makes it possible divide set subcircuits into classes. problem reduced checking isomorphism labeled graphs defining level by canonizing them comparing canonical labeling. resulting two-level presented SPICE format. Results. implemented C++ as part circuit decompilation program case without predetermined cell library. method canonization used: recognize among functionally that implement elements; split not recognized elements classes ones; verify results extraction hierarchical at transistor-logic relative Conclusion. has been tested practical transistor-level circuits. Experiments indicate this tool fast enough process with more than one hundred thousand transistors few minutes personal computer.

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ژورنال

عنوان ژورنال: Informatika

سال: 2022

ISSN: ['2798-2505']

DOI: https://doi.org/10.37661/1816-0301-2022-19-3-25-39